1. Field of the Invention
The present invention generally relates to the viewing of circuit components of a circuit design database and more particularly relates to a method and apparatus for efficiently viewing a selected list of components using a database editor tool.
2. Description of the Prior Art
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer, and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Such software is typically implemented as part of an electronic design automation (EDA) system. Specifically, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form. Chip designers generally employ hierarchical design techniques to determine the appropriate selection and interconnection of logic and/or memory devices which will enable the chip to perform the desired function. These techniques involve describing the chip's functionality at various levels of abstraction, ranging from the most general function performed by the chip to the precise functions performed by each logic and/or memory element on the chip.
A common method for specifying the integrated circuit design is the use of hardware description languages. This method allows a circuit designer to specify the circuit at the register transfer level (also known as a “behavior description”). Using this method, the circuit is defined in small building blocks. The names of the building blocks are specified by the circuit designer. Thus, they usually are logical names with specific functional meaning.
Encoding the design in a hardware description language (HDL) is a major design entry technique used to specify modern integrated circuits. Hardware description languages are specifically developed to aid a designer in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way.
Another common method for specifying the integrated circuit design is the use a schematic capture tool. A schematic capture tool allows the circuit designer to directly enter the schematics for the circuit design. Unlike a hardware description language, the resulting schematics often completely specify the logical and functional relationships among the components of the design.
It is useful to distinguish between those components of an integrated circuit design called cells, provided by a silicon chip vendor as primitive cells (i.e., leaf candidates), and the user-defined hierarchy blocks built upon them. One way is to speak of a “cell library” vs. a “design library” as two separate libraries, both of which are available to subsequent designs. Alternatively, at least initially, a design library contains a cell library. A cell library is a database containing detailed specifications on the characteristics of each logical component available for use in a design. Initial cell library contents are usually provided by the chip vendor. The components in the cell library are identified by the generic description of the component type. For example, the term “NAND” for a NAND gate is its type description and distinguishes this component from others such as OR gates, flip-flops, multiplexors, and so on. A two-input NAND gate might be of type 2NAND. When a 2NAND component is specified as part of a given circuit design, it is given an instance name, to distinguish it from all other 2NAND gates used in the circuit. The instance name typically includes the instance names of all parent instances by concatenation when defining the instance in the context of the chip.
The user-defined blocks can then be used to design larger blocks of greater complexity. The user-defined blocks are added to the design library, which grows from the additions of new design modules as the design evolves. The top level of the design hierarchy may be a single block that defines the entire design, and the bottom layer of the hierarchy may consist of leaf cells, the cells (i.e., the logical components) that were originally provided in the cell library. Note that the hierarchy is typically structured as a special kind of a graph called a tree. This resulting data structure is called a detailed (or gate-level) description of the logic design.
The generation of the detailed description is often accomplished by logic design synthesis software for HDL entry. The logic design synthesis software generates a gate-level description of user-defined input and output logic, and also creates new gate-level logic to implement user-defined logical functions. Constituent parts of new gate-level logic created during each pass through the logic design synthesis software are given computer-generated component and net names. Each time the logic design synthesis software is executed for the integrated circuit design, the component and net names which are generated by the software, and not explicitly defined by the user, may change, depending on whether new logic has been added to or deleted from the integrated circuit design. Typically, the logic design synthesis software is executed many times during the integrated circuit design process, because errors may be detected during the simulation and testing phases of the design cycle and then fixed in the behavioral description.
The output of the design capture and synthesis tools is a logic design database which completely specifies the logical and functional relationships among the components of the design. Once the design has been converted into this form, it may be optimized by sending the logic design database to a logic optimizer tool implemented in software. The logic optimizer may remove logic from the design that is unnecessary, or otherwise improve the overall efficiency of the design. It is noted, however, that this action typically affects the component and net names generated by the logic synthesis tool.
It is also necessary to verify that the logic definition is correct and that the integrated circuit implements the function expected by the circuit designer. This verification is currently achieved by estimated timing and simulation software tools. The design undergoes design verification analysis in order to detect flaws in the design. The design is also analyzed by simulating the device resulting from the design to assess the functionality of the design. If errors are found or the resulting functionality is unacceptable, the designer modifies the behavior description as needed. These design iterations help to ensure that the design satisfies its requirements. As a result of each revision to the design, the logic design synthesis-generated component and net names may completely change. Further, the changes made by the logic optimizer may not be precisely known. Thus, the EDA tools downstream in the design process from the logic design synthesis software must be re-executed on the entire design.
After timing verification and functional simulation has been completed on the design, placement and routing of the design's components is performed. These steps involve assigning components of the design to locations on the integrated circuit chip and interconnecting the components to form nets. This may be accomplished using automated place and route tools.
After the circuit design is successfully placed and routed, the design is again verified for correctness. This may include a full verification step, including timing verification and design rule checks (DRCs). Timing verification may be accomplished by extracting parasitics from the layout of the circuit design, and providing the parasitics to a timing analysis tool. The timing analysis tool may use the parasitics, along with the timing models for each cell in the design, to identify any timing problems therein.
Design rule checks (DRCs) are typically performed by a DRC tool. Design rules are typically technology dependent, and are often provided by the integrated circuit manufacturer that will “process” the integrated circuit. Design rules may include spacing rules, overlap rules, minimum dimension rules, etc. For example, the minimum metal width for a particular metal layer may be 1.0 μm, and the minimum spacing between the metal traces may be 1.2 μm. These are only meant to be illustrative. Typical design rules are complex and often define both inter-layer rules as well as between-layer rules. DRC tools typically compare the layout of the circuit design with the predefined design rules, and report any design rule violations found therein.
Modern integrated circuits often contain tens of thousands of cells. There may be many errors found by the full verification process including both timing related problems and design rule violations. In either case, the circuit design must typically be edited to correct the detected violations. This may require the use of a database editor tool. The particular database editor tool that is used by a circuit designer may vary, depending on the type of violations. For example, if a logic error is detected, the circuit designer may use a schematic editor to correct the original schematics (if the logic is entered via a schematic capture tool rather than a HDL). Similarly, if a timing error is detected, a cell substitution list may be generated, and each cell substitution may be made in a physical database editor such as a placement tool. Likewise, if a design rule violation is detected, a physical database editor may be used to edit the physical database to correct the violation.
In all of the above cases, it may be important to view specific pre-identified cells or components that are involved in the detected errors. Once a circuit designer can view an offending cell, an editing function of the database editor tool may be used to correct the violation.
In prior art database editor tools, this correction process could be tedious and time-consuming because there was not an efficient method for locating the cells or nets involved in the violations. A circuit designer typically had to manually locate the violations by panning through the design using the database editor's graphics window. Even when the exact location of the violation was known, navigating to that location could be slow, particularly since the graphics terminal may be manipulating files that contained tens of thousands of objects. Further, once the violation was found, the database editor was not set to the proper level in the design hierarchy to immediately allow an editing function on the offending cell or component.